Researchers from the National Research University Higher School of Economics (HSE University) have developed an algorithm for designing communication networks within a microchip, which accelerates the formation of defect-tolerant connections between computing nodes. As reported to TASS by the university's press service, the application of this approach will increase the reliability of microprocessors.

The algorithm's operating principle can be compared to a car navigator: if the usual road is blocked, the system immediately looks for a detour. The development combines eight local algorithms and allows for selecting data transmission routes 16–22 times faster than benchmark global methods. Moreover, the selected paths differ from optimal ones by only 1.64% even with a significant number of damaged nodes.

Alexander Romanov, head of the educational laboratory for computer-aided design at MIEM HSE, explained that the team plans to test the algorithm on real microchips and evaluate its impact on power consumption and data transfer speed.

Modern processors and systems-on-chip consist of thousands of specialized blocks that exchange data through communication networks. Random manufacturing defects require laying alternative routes. The new algorithm accelerates this process and allows for designing chips capable of operating in complex conditions and tolerating a large number of manufacturing defects.